Field of the Invention
The invention pertains to a fabrication method for a DRAM cell configuration, that is to say a dynamic random access memory cell configuration, whose memory cells each comprise a transistor and a capacitor.
In such a DRAM cell configuration, the information of a memory cell is stored in the form of a charge on the capacitor. The transistor and the capacitor of the memory cell are connected to one another in such a way that when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line.
Endeavors are generally made to produce DRAM cell configurations with a high packing density, that is to say a small space requirement per memory cell.
European published patent specification EP 0 852 396 (see commonly assigned U.S. Pat. Nos. 5,937,296 and 6,150,210) describes a DRAM cell configuration in which, in order to increase the packing density, a transistor of a memory cell is arranged above a storage capacitor of the memory cell. Active regions of the memory cells are in each case surrounded by an insulating structure arranged in a substrate. A depression is produced in the substrate for each memory cell, a storage node of the storage capacitor being arranged in the lower region of the depression and a gate electrode of the transistor being arranged in the upper region of the depression. An upper source/drain region, a channel region and a lower source/drain region of the transistor are arranged one above the other in the substrate. The lower source/drain region is connected to the storage node at a first sidewall of the depression. The insulating structure adjoins a second sidewallxe2x80x94opposite the first sidewallxe2x80x94of the depression, with the result that the storage node does not adjoin the substrate there. A bit line adjoins the upper source/drain region and runs above the substrate. In order to fabricate the DRAM cell configuration, firstly the insulating structure is produced. The bit line is produced on a surface of the substrate. The upper source/drain region is produced by the diffusion of dopant from the bit line into the substrate. The depression is produced in a manner adjoining the insulating structure. Sidewalls of the depression are provided with a capacitor dielectric. The depression is filled with doped polysilicon up to a first height, which lies in the region of the insulating structure. Uncovered parts of the capacitor dielectric are removed. Afterward, the depression is filled with doped polysilicon up to a second height, which is higher than the first height and lies in the region of the insulating structure, with the result that the polysilicon forms a storage node which adjoins the substrate at the first sidewall of the depression between the first height and the second height. The lower source/drain region is formed by the diffusion of dopant from the storage node into the substrate.
The object of the present invention is to provide a method of producing a DRAM cell configuration which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which process leads to a DRAM cell having a higher packing density in comparison with the prior art.
With the above and other objects in view there is provided, in accordance with the invention, a method of fabricating a DRAM cell configuration, which comprises the following steps: producing a depression for a capacitor of a memory cell of the DRAM in a substrate;
producing in the depression an insulation and a storage node of the capacitor, wherein the capacitor is at least partly isolated from the substrate by the insulation;
producing a spacer of silicon above the storage node in the depression along sidewalls of the depression, by deposition, etching back, and inclined implantation of silicon, wherein a first part of the spacer and a second part, opposite the first part, of the spacer are doped differently;
patterning the spacer by removing one of the first part of the spacer and the second part of the spacer utilizing the different doping thereof;
altering the insulation and a first part of the storage node disposed under the removed part of the spacer, such that either the first part of the storage node or a second part of the storage node disposed under the remaining part of the spacer, adjoins the substrate, and thereby utilizing the patterned spacer as a mask;
producing a transistor of the memory cell such that a first source/drain region is formed in the substrate adjoining the storage node;
producing and connecting a word line to a gate electrode of the transistor; and
producing a bit line running transversely with respect to the word line and connecting the bit line to the memory cell.
In other words, the above objects are satisfied with the method of fabricating a DRAM cell configuration, in which a depression is produced in a substrate for a capacitor of a memory cell of the DRAM cell configuration. An insulation and a storage node of the capacitor, which is at least partly isolated from the substrate by the insulation, are produced in the depression. By deposition, etching back and inclined implantation of silicon, a spacer made of silicon is produced above the storage node in the depression along sidewalls of the depression, in which a first part of the spacer and a second partxe2x80x94opposite to the first partxe2x80x94of the spacer are doped differently. The spacer is patterned by either the first part of the spacer or the second part of the spacer being removed by utilizing their different doping. A first part of the storage node, said first part being arranged under the removed part of the spacer, and the insulation are altered in such a way that either the first part of the storage node or a second part of the storage node, said second part being arranged under the remaining part of the spacer, adjoins the substrate, the patterned spacer serving as a mask. A transistor of the memory cell is produced in such a way that a first source/drain region is formed in the substrate in a manner adjoining the storage node. A word line is produced and connected to a gate electrode of the transistor. A bit line running transversely with respect to the word line is produced and connected to the memory cell.
The spacer is composed, for example, of polysilicon or amorphous silicon.
The patterned spacer acts as a mask in that the remaining part of the spacer protects the second part of the storage node from process steps.
Since the storage node does not adjoin the substrate both with its first part and with its second part, an adjacent memory cell can be arranged in direct proximity to the depression, without leakage currents occurring between the storage node and the adjacent memory cell. The storage node is isolated from the adjacent memory cell by the insulation in the depression. An insulation structure outside the depression which isolates the storage node from the adjacent memory cell is not necessary, with the result that the DRAM cell configuration can have a particularly high packing density. The single-sided alteration of the storage node and of the insulation is effected in a self-aligned manner, that is to say without the use of a mask to be aligned. This is a major advantage with regard to a high packing density since there is no need to take account of a space requirement for alignment tolerances.
Since insulation structures which are arranged outside the depression and reach down into regions of the first source/drain regions of the transistors of the memory cells are not required, the invention makes it possible to fabricate a DRAM cell configuration in which channel regions of the transistors are electrically connected to one another or to the substrate. In this case, charge carriers generated in the channel region can flow away, thereby avoiding what are referred to as floating body effects, such as, for example, an alteration of the threshold voltage of the transistor.
To that end, it is advantageous if, after the completion of the storage node, dopant diffuses, during a heat-treatment step, from the storage node into the substrate and forms the first source/drain region there. In this case, in particular, the storage node is at least partly composed of doped polysilicon, for example.
As an alternative, the first source/drain region is produced by patterning a doped layer buried in the substrate. The doped layer is patterned through the depressions and through isolation trenches which cut through the doped layer. In this case, the channel regions of the transistors are electrically isolated from one another and from the substrate.
It lies within the scope of the invention for the storage node and the insulation firstly to be produced in such a way that both the first part of the storage node and the second part of the storage node adjoin the substrate. The first part of the storage node is subsequently removed using the patterned spacer as a mask. The insulation is enlarged in such a way that it replaces the first part of the storage node. Consequently, only the second part of the storage node adjoins the substrate.
A method is described below by means of which the storage node and the insulation are initially produced in such a way that both the first part of the storage node and the second part of the storage node adjoin the substrate:
After depression has been produced, the insulation is produced in such a way that it covers sidewalls and a bottom of the depression. Conductive material is deposited and etched back down to a first height. Uncovered parts of the insulation are subsequently removed, with the result that the insulation likewise reaches only as far as the first height. By depositing further conductive material and etching it back as far as a second height, which lies above the first height, the storage node is produced, which adjoins the substrate between the first height and the second height, while it is isolated from the substrate by the insulation below the first height.
After the removal of the first part of the storage node, the insulation can be enlarged by depositing insulating material and etching it back.
It lies within the scope of the invention for the storage node and the insulation firstly to be produced in such a way that neither the first part nor the second part of the storage node adjoin the substrate. Using the patterned spacer as a mask, the insulation is removed in the region of the first part of the storage node. By depositing conductive material and etching it back, the first part of the storage node is subsequently enlarged, with the result that it adjoins the substrate. In this case, only the first part of the storage node adjoins the substrate.
To that end, after the production of the depression, the insulation can firstly be produced in such a way that it covers the sidewalls and the bottom of the depression. Conductive material is subsequently deposited and etched back. The storage node thereby produced initially adjoins the substrate neither with its first part nor with its second part.
Only a few possibilities will be described with regard to how the spacer can be patterned by utilizing the different doping of the first part and of the second part:
If the first part of the spacer is doped with n-doping ions, then the first part of the spacer can be etched away selectively with respect to the second part of the spacer. A suitable etchant is HNO3+COOH+HF, for example. Consequently, the removed part of the spacer is the first part of the spacer. The remaining part of the spacer is the second part of the spacer. In this case, the second part of the spacer is preferably essentially undoped.
If the first part of the spacer is doped with p-doping ions, then the second part of the spacer can be etched away selectively with respect to the first part of the spacer. A suitable etchant is choline or KOH, for example. Consequently, the removed part of the spacer is the second part of the spacer, while the remaining part of the spacer is the first part of the spacer. In this case, the second part of the spacer is preferably essentially undoped.
If, during the implantation, the spacer is not implanted throughout its vertical extent, then a further part of the spacer is arranged under the first part of the spacer. After the removal of the first part of the spacer, this further part of the spacer continues to be arranged above the first part of the storage node. In order to uncover the first part of the storage node in order that it can be altered, the further part of the spacer is removed. This can be done by anisotropic etching, the remaining part of the spacer being attacked at the same time. However, since the remaining part of the spacer has a larger vertical extent than the further part of the spacer, even after the removal of the further part of the spacer the patterned spacer covers the second part of the storage node and consequently protects it.
A further possibility for patterning the spacer consists, in the case of an n-doped first part of the spacer, in firstly carrying out a thermal oxidation. Since the first part of the spacer has a higher concentration of n-doping ions than the second part of the spacer, the oxide grows more thickly on the first part of the spacer than on the second part of the spacer. The oxide is subsequently etched until the second part of the spacer is uncovered. Since the oxide on the first part of the spacer is particularly thick, a part of the oxide remains on the first part of the spacer and protects it. During the patterning of the spacer, silicon is etched selectively with respect to the oxide, with the result that the second part of the spacer is removed.
The same principle can be employed if the first part of the spacer is implanted with nitrogen or with oxygen. In the case of implantation with nitrogen, the oxide grows more slowly on the first part than on the second part. In the case of implantation with oxygen, the oxide grows more slowly on the second part than on the first part.
In order to ensure that, during the implantation of the first part of the spacer, the dopant reaches that edge of the spacer which faces the sidewall, it is advantageous to carry out a heat-treatment step during which the dopant can diffuse.
In order to simplify the process and in order to increase the process reliability, it is advantageous to use the remaining part of the spacer as a spacer for the gate electrode. In this case, after the completion of the storage node, the remaining part of the spacer is removed and at least partly replaced by the gate electrode. The fabrication process is particularly simple since the gate electrode is produced in a self-aligned manner, that is to say without the use of a mask to be aligned. To ensure that the gate electrode is electrically insulated from the storage node, an insulating layer is produced on the storage node before the spacer is produced. The spacer is produced on the insulating layer. Consequently, this insulating layer also isolates the gate electrode from the storage node. In order to uncover the first part of the storage node so that it can be altered, an uncovered part of the insulation layer is removed after the patterning of the spacer.
A second source/drain region of the transistor is produced above the first source/drain region of the transistor, with the result that the transistor is formed as a vertical transistor. Such a DRAM cell configuration can have a particularly high packing density on account of the vertical formation of the transistor. Since the gate electrode is formed above the second part of the storage node, in this case the first source/drain region should adjoin the second part of the storage node. Thus, the second part of the storage node adjoins the substrate, while the first part of the storage node does not adjoin the substrate. Since the gate electrode is spaced apart from parts of the substrate which are arranged in the region of the first part of the storage node, the formation of a capacitance between the gate electrode and the substrate is prevented.
By way of example, the word line can be produced above the substrate and adjoin an upper part of the gate electrode. The insulation is enlarged, for example, by depositing insulating material and etching it back until the remaining part of the spacer is uncovered.
In the case where the remaining part of the spacer serves as a spacer for the gate electrode, it is advantageous if the remaining part of the spacer is not attacked during the patterning of the spacer. In particular when the first part of the spacer is removed selectively with respect to the second part of the spacer, it is advantageous if no further part of the spacer is arranged under the first part of the spacer. In other words, the first part of the spacer encompasses the entire vertical extent of the spacer. In this case, the inclined implantation is effected at an angle at which the spacer is implanted throughout its vertical extent.
In the case where such inclined implantation is not carried out, in other words lower regions of the spacer are not implanted, it is advantageous to carry out a heat-treatment step, during which dopant diffuses from the first part of the spacer into the underlying further part of the spacer. As a result, the further part of the spacer can likewise be etched away selectively with respect to the second part of the spacer, with the result that the second part of the spacer is not attacked.
In order to prevent, in the process, dopant from diffusing from the first part of the spacer into the second part of the spacer, it is advantageous to separate the spacer before the heat-treatment step, with the result that the first part of the spacer is electrically isolated from the second part of the spacer.
Such separation can be effected for example by masked etching of the spacer.
In order to increase the process reliability, it is advantageous, however, if the separation is effected in a self-aligned manner, that is to say without the use of a mask to be aligned. To that end, a first auxiliary layer can be produced on the substrate, auxiliary trenches which essentially run parallel to one another and are arranged next to one another being produced in said auxiliary layer, which auxiliary trenches do not cut through the first auxiliary layer. The depressions of the memory cells are produced in the auxiliary trenches. After the production of the spacer, a second auxiliary layer made of a first material, which can be etched selectively with respect to silicon, is deposited essentially conformally, the second auxiliary layer being so thin that the auxiliary trenches are not filled. A second material, which can be etched selectively with respect to the first material, is deposited and etched back until the second material is present as a strip-type structure only within the auxiliary trenches. Uncovered parts of the second auxiliary layer are removed selectively with respect to the second material, with the result that the spacer is partly uncovered. Silicon is subsequently etched until the spacer is separated. The separated spacer is subsequently patterned.
It is advantageous for the first auxiliary layer and the second auxiliary layer, which act as a mask during the separation of the spacer, to be used in order to alter the storage node in such a way that, before the alteration of its first part, it adjoins the substrate only with its first part and with its second part. To that end, using the first auxiliary layer and the second auxiliary layer as a mask, parts of the storage node are removed and replaced by insulating material. As an alternative, it is possible to produce isolation trenches which reach down into the region of the storage node, where they isolate the storage node from the substrate.
If the remaining part of the spacer serves as a spacer for the gate electrode, then the separation of the spacer brings about a restriction of the channel width of the transistor. This is advantageous in particular when the depression has curved sidewalls. As is known, the quality of a gate dielectric grown by thermal oxidation is poorer on curved areas than on planar areas. Consequently, it is advantageous to limit the channel to planar sections of the sidewalls of the depression.
A method is described below with regard to how the second source/drain region can be produced:
After the alteration of the insulation and of the storage node, insulating material is deposited and etched back until the remaining part of the spacer is uncovered. The remaining part of the spacer is removed. A third auxiliary layer is deposited to a thickness such that the auxiliary trenches are not filled. A third material is deposited and etched back until the third material is present only within the auxiliary trenches and forms a respective strip-type mask in the auxiliary trenches. Uncovered parts of the third auxiliary layer are removed selectively with respect to the mask. Parts of the first auxiliary layer which are arranged outside the mask are removed and parts of the substrate which are arranged underneath are uncovered. The substrate is then etched selectively with respect to the mask, with the result that isolation trenches are produced. The mask and first auxiliary layer are then removed. The second source/drain regions are produced in parts of the substrate which are arranged under the mask. The isolation trenches are produced in such a way that they are deeper than the second source/drain regions. The second source/drain regions are arranged in the region of the auxiliary trenches and in each case between two of the depressions. The second source/drain regions are isolated from one another by the depressions and by the isolation trenches.
The second source/drain regions can be produced by implantation after the removal of the mask and of the first auxiliary layer. As an alternative, the second source/drain regions are produced by patterning a doped layer produced in the region of the surface of the substrate, by this doped layer being patterned through the depressions and through the isolation trenches.
In order that a dimension of the second source/drain regions corresponds to the channel width, it is advantageous if a thickness of the third auxiliary layer corresponds to the sum of the thickness of the spacer and of the second auxiliary layer.
In order to simplify the process and in order to increase the process accuracy, it is advantageous if the depressions are produced in a self-aligned manner in the auxiliary trenches in such a way that their horizontal cross section in each case reaches from one sidewall to the other sidewall of the corresponding auxiliary trench.
To that end, by way of example, a first mask layer is deposited over the first auxiliary layer before the latter is patterned, and a second mask layer is deposited over said first mask layer. The auxiliary trenches are subsequently produced, the first mask layer and the second mask layer also being cut through. The first insulating structures are subsequently produced by material being deposited and etched back until the second mask layer is uncovered. With the aid of a strip-type photoresist mask whose strips run transversely with respect to the auxiliary trenches, the first insulating structures are etched selectively with respect to the photoresist mask and with respect to the second mask layer until the auxiliary trenches are partly uncovered. The uncovered parts of the first auxiliary layer at the bottoms of the auxiliary trenches are removed until the substrate is partly uncovered. The uncovered parts of the substrate are subsequently etched, thereby producing the depressions. The first mask layer and the first insulating structures serve as a mask in this case.
In order to avoid leakage currents on account of the formation of local field spikes at edges of the depressions, it is advantageous to produce rounding elements which likewise serve as a mask during the production of the depressions. To that end, material of the first mask layer is deposited, etched back and subsequently etched isotropically, with the result that the first material rounds off edges which are formed within the first auxiliary layer. The depressions that are subsequently produced have no edges.
The insulation in the depressions serves at least partly as a capacitor dielectric of the capacitors. Capacitor electrodes of the capacitors are formed as doped regions in the substrate in a manner adjoining the capacitor dielectric. The capacitor electrodes may be contiguous and form a common capacitor electrode for all the capacitors. The capacitor electrodes may be produced for example by the outdiffusion of dopant from a dopant source introduced into the depressions. As an alternative, the capacitor electrodes are produced from a doped layer buried in the substrate.
It lies within the scope of the invention for the insulation to be made particularly thick above the capacitor electrode.
The spacer is produced by depositing silicon and etching it back. The inclined implantation can be carried out before or after the etchback.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method of fabricating a DRAM cell configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.